A single cosmic ray particle passing through an integrated circuit can generate an electrical transient that interferes with the normal operation of the circuit. The disruption caused in an integrated circuit by a cosmic ray is termed a single event upset. Single event upsets include changes of state (i.e., bit flips) in memory elements, device latchups and dielectric breakdowns. Latchup occurs when a memory element is stuck in one state and does not respond to a write operation. A latched-up element can be restored to normal function by powering down and then reapplying power, if the latch-up has not caused thermal damage to the device. Dielectric breakdown refers to the creation of a conductive path through an insulator (e.g., silicon nitride) layer. The high current and resulting thermal runaway resulting from a dielectric breakdown can result in the permanent failure of an integrated circuit. Bit flips are less catastrophic events, and the memory element in which the flip occurred can typically be rewritten to eliminate all trace of the upset. Bit flip errors may occur not only in memory devices such as RAM, but also in other integrated circuits that include data storage elements such as flip-flops, registers, counters, and microprocessors. As the speed and packaging density of spaceborne computers, memories, and other integrated circuits improve, the susceptibility of these components to cosmic ray upset increases. Such damage is occurring in the MSI and LSI devices used in the present generation of spacecraft, because no protection against cosmic ray effects was included in their electronic designs.
Cosmic rays are high energy ions, protons and electrons that have a galactic origin. The cosmic ray flux may strike an orbiting spacecraft from all directions and at all hours, and is not related to the position of the spacecraft with respect to the sun or the earth. The cosmic ray particle most likely to produce a single event upset is a heavy ion, i.e., an atomic nucleus with an atomic number greater than two. When an energetic heavy ion (e.g. Fe) particle passes through a semiconductor material, the particle loses energy by a process that creates electron-hole pairs in the semiconductor. Typically, the particle penetrates through the semiconductor material in a straight line path. Electrical interactions result in energy transfer to electrons, producing secondary electrons with a spectrum of energies and traveling in random directions. The secondary electrons spread from the original particle path for a distance of up to a few microns, losing energy by creation of additional electron-hole pairs. The result is a cylindrically shaped path of ionization through the semiconductor, with a diameter on the order of 1-5 microns and with an ionization intensity that varies approximately as 1/r.sup.2 with distance away from the path center. The process is very rapid, on the order of picoseconds, and may be treated as instantaneous deposition of energy and charge along the path traveled by the heavy ion. In silicon, the creation of each electron-hole pair requires 3.6 electron volts. A loss of 3.6 MeV by a cosmic ray particle will therefore result in the creation of one million electron-hole pairs, or 0.16 picocoulombs.
Integrated circuits represent a bit of binary data as the presence or absence of charge at a particular node (e.g., at a MOS capacitor). The quantity of charge at a node that differentiates between a binary one and a binary zero may be defined as the critical charge. This critical charge is determined by node capacitance and the threshold voltages of associated circuit elements. Typical values for the critical charge in current integrated circuits are 0.01 to 1.0 picocoulombs. The basic mechanism for cosmic ray induced bit errors is the neutralization of the critical charge by the collection at the node of ionization induced electrons or holes. Most electrons and holes that are generated by heavy ion induced ionization within depletion regions surrounding nodes will be separated by the electric field at the node, with electrons being swept to the positive potential, and holes being swept to the negative potential. Charges generated outside the depletion region may diffuse to the edge of the depletion region and be swept into the node.
The rate at which an ion loses energy in passing through a material is described by the linear energy transfer or LET for that ion. For typical diffusion rates, node dimensions and critical charges, an LET on the order of a few MeV/micron is required to deposit the critical charge in the path through the node. The magnitude of the critical charge is a function of circuit parameters, and particularly of the size of the node. Unfortunately, the critical charge decreases rapidly as the feature size of integrated circuits decreases. For example, in many classes of integrated circuits, the critical charge varies as the inverse square of the feature size of a memory cell. As today's VSLI circuits evolve into VHSIC circuits in the future, the feature size will continue to decrease, and susceptibility to single event upsets will become an increasing important property of spaceborne electronics.
It is known that shielding is an ineffective solution to the problem of the single event upsets caused by heavy cosmic rays. The problem is that the amount of shielding required to exclude such cosmic rays would impose an impossible weight penalty on a spacecraft. The use of parallel and redundant systems (e.g., with majority voting) imposes a similar weight penalty, and also poses the problem of how to protect the "voting" electronics. As a result, the best approach to the single event upset problem is to devise integrated circuits that are relatively immune to such upsets. As described above, susceptibility to single event upsets will generally increase with improvements in desirable circuit parameters such as speed, performance, small feature size, high packaging densities and low power consumption. Knowing the susceptibility of an integrated circuit to single event upsets thereby permits a circuit designer to balance single event upset susceptibility with speed and performance in the design of spacecraft electronics.
Theoretical calculations of device susceptibilities are complicated by the fact that charge collection at an integrated circuit node is a complex process that is highly dependent on device structure and bias levels. Furthermore, in multilayer integrated circuits, several nodes may be penetrated by a single cosmic ray particle. Thus, to date, actual testing has proved to be the most effective way to determine device susceptibility. In the past, the testing of integrated circuits for susceptibility to heavy cosmic ray particles has been carried out almost exclusively at high-energy accelerators, such as cyclotron or tandem Van de Graaff accelerators. The cost of using these facilities is high, and the facilities are often located at remote locations. Although laboratory sources exist for protons and alpha particles, no laboratory source can effectively produce high energy heavy ions of the type found in cosmic rays. The collection of data concerning the susceptibility of integrated circuits to the heavy ion component of cosmic rays has therefore been a slow and difficult process.